The present invention relates generally to the generation of periodic signals, and more particularly to delay locked loop circuits (DLLs) having reduced signal lock time, and to integrated circuit memories including such DLLs.
Many high speed electronic systems possess critical timing requirements which dictate the need to generate a periodic clock waveform that possesses a precise time relationship with respect to some reference signal. The improving performance of computing integrated circuits (ICs) and the growing trend to include multiple computing devices on the same board present challenges with respect to synchronizing the timing of all the components.
While the operation of all components in a system should be highly synchronized (i.e., the maximum skew or difference in time between the significant edges of the internally generated clocks of all the components should be minute), it is not enough to feed the reference clock of the system to all the components. This is because different chips may have different manufacturing parameters which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Conventionally, synchronization, that is forcing an on-chip clock signal to match an external clock signal, or forcing two clock signals from different functional blocks of a circuit to be aligned, is achieved by using phase locked loops (PLL) or delay locked loop (DLL) circuits to detect the phase difference between clock signals of the same frequency and to produce a signal related to the phase difference between the signals. By feeding back the phase-difference-related signal to control an adjustable delay chain, the timing of one clock signal is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal. Analog delay locked loops introduce analog design considerations into digital circuits, and are therefore less than desirable in digital circuits. Digital delay locked loops use an adjustable delay chain. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Oscillator noise is not a factor in a DLL, and jitter is reduced. However, any ripple on the output of the loop filter will cause jitter.
In a conventional delay locked loop (DLL), a clock input buffer accepts a clock input signal and transmits the signal to one or more delay chains, as shown in FIG. 1. The delay of the delay path is increased from a minimum setting until the edge of the delayed reference clock is eventually time-shifted just past the next corresponding edge of the reference clock. A digital phase detection circuit is employed to control the delay line propagation delay so that the delayed clock remains synchronized with reference clock.
A diagram of a typical digital DLL 100 is illustrated in FIG. 1. An input clock signal, CLK IN, is received via a buffer 102. The buffer 102 provides a buffered clock signal to delay line 108 and phase detector 104, and is coupled as well to shift register 106. The end of the delay line 108 is coupled to buffer 110 through which an output clock signal is produced. The output clock signal is buffered through a buffer 112 to produce a feedback clock signal which is provided to the phase detector 104. In operation, the phase detector 104 determines if a phase difference exists between the buffered input and feedback clock signals. The phase difference determines an appropriate shift in the buffered input clock signal via adjustment of shift bits in the shift register 106 to select sufficient delay in the delay line 108.
Multiple delay chains may be used in further prior art configurations. In such configurations, a second delay chain is connected to dummy circuitry, including a dummy clock buffer and load capacitance, that matches the delay of the internal clock path of the actual circuit. Such circuitry includes a divider which divides down the external clock signal to produce a divided down external signal. A second signal is the signal at the output of dummy delay chain. A third signal generated inside phase comparator is a one-delay-unit-delayed signal. If the second and third signals each go high before the divided down external signal goes low, the output clock is too fast. The phase comparator outputs a shift left (SL) command to the shift register. The shift register then shifts the tap point of the delay chains by one step to the left, increasing the delay. Conversely, if both the second and the third signals go high after the divided down clock signal goes low, the output clock is too slow, and the phase comparator outputs a shift right (SR) command to the shift register. The shift register then shifts the tap point of the delay chains by one step to the right, decreasing the delay. If the divided down clock signal goes low between the time the second and third signals go high, the internal cycle time is properly adjusted and no shift command is generated. The output of the internal clock path in this case coincides with the rising edge of the external clock and is independent of external factors such as ambient temperature and processing parameters.
Conventional DLLs suffer from numerous drawbacks. One such drawback occurs in the event of power-up of the DLL or after a pause in the input driving the DLL. In a conventional DLL, the logic is randomly initialized to unknown values at power-up or after a pause. This problem is typically resolved in conventional DLLs by using initialization circuitry to power-up the DLL at some predetermined value. The predetermined value most often used is to set the shift bits of the delay chain of the DLL to binary zeros (xe2x80x9c0xe2x80x9ds). A delay chain of 0s in the DLL is a minimum delay setting. The initial lock sequence then proceeds through the delay chain, one element at a time, until a lock is achieved. Using this conventional locking scheme, a DLL with a delay chain of, for example, 100 elements could require as many as 100 cycles to achieve a lock. An optimum predetermined setting of half 1s and half 0s could be used. However, depending on the length of the delay chain of DLL, such a setting could still require a large number of cycles, up to 50, before a lock is achieved.
Another drawback of many conventional DLLs is that they are inherently inaccurate. This inaccuracy is due to the fact that they compare a divided down version of the input clock signal, rather than the actual input clock signal, with the output clock signal.
There is a need, therefore, to improve the performance of DLLs by reducing the number of cycles required to achieve a lock after power-up or a pause in input cycles.
In one embodiment, a method of improving synchronization time in a delay locked loop (DLL) includes propagating a first input clock pulse through a delay line having a number of delay elements, and toggling a number of shift bits, each shift but corresponding to one of the delay elements, as an edge of the first input pulse passes each delay element. This embodiment further includes propagating a second input clock pulse through the delay line, and re-toggling a portion of the shift bits in response to an edge of the second pulse. The re-toggling is halted when the edge of the first pulse reaches an end of the delay line, DLL synchronization is started at a transition between toggled and re-toggled shift bits.
In another embodiment, a method for reducing lock time in a delay locked loop (DLL) includes measuring a length of an input clock period relative to a path length through the DLL, and estimating a starting point for a lock sequence based upon a phase difference between two consecutive clock pulses passed through the DLL.
In yet another embodiment, delay locked loop (DLL) includes a delay line having a number of delay elements and a corresponding number of shift bits in a shift bit register. Each shift bit is connected to one of the delay elements to toggle each shift bit on a rising edge of a clock signal. The DLL further includes delay line circuitry to pass two consecutive rising clock signal edges to the delay line, and edge detection circuitry at an output end of the delay line to halt toggling of the shift bits upon detection of the first edge at the output end of the delay line.
In still another embodiment, an integrated circuit includes first and second sub-circuits connected to synchronize to an external clock, and a delay locked loop (DLL) connected to synchronize the first and the second sub-circuits.
Other embodiments are described and claimed.